Intel Presents the 22nm Technology

24th September, 2009 by caitas
Tags: 22nm Processor, Hardware, Intel, News, Processors, Technology

Intel Company recently revealed on its Develop Forum the first cases in which chips manufactured in a 22 nanometer process were put to work. This technology is smaller than the 32 nanometer process which will soon start producing parts. The 22 nanometer technology is expected to be more performing than the latter one and develop smaller elements that fill the same space with a larger number of parts. One single chip manufactured with the 22 nanometer process is as small as a fingernail and comprises almost 2.9 billion transistors and approximately 45.5 MB or 364 megabits of static RAM.

The semiconductor organization did not specifically state when the processors developed with the 22 nm technology would be available on the market, but it is largely known that the company adopts a certain strategy that is to firstly launch a smaller operation for developing the products and then, secondly, introduce a new approach to utilize that specific process. Thus, considering the fact that the 32 nm is going to be available as a full scale operation sometime near this year`s end, we may conclude that the 22nm technology will be used starting with the year 2011.

Around the same time, the organization repeated the plans for the SandyBridge which is the approach that will use the 32nm technology and manufacture products. This architecture includes a new graphics core into the paint of the chip and, thus, increases very much the efficiency of the included video compared to the different graphics developed by Nehalem. Furthermore, these creations might also comprise Advanced Vector Extensions, a new collection of instructions that can support 256-bit data compared to the SSE4 that handles just 128-bit data. This set of extensible instructions can also process up to four tasks at one time.

Rumors that arose in the past also stated that Sandy Bridge will enable even eight cores in just one processor and for each chip a 16MB of Level 3 cache.

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